Srivatsa Vasudevan is an experienced verification engineer working in Silicon Valley. He has extensive verification experience, having helped tape out many devices at Philips Semiconductor, Ciena Corp, Texas Instruments and Qualcomm. His expertise is in verification methodology, simulation performance and helping teams navigate complex technical challenges. He is familiar with all activities in functional verification including test case, test plan and test bench development and simulation performance tuning for large SOC designs with emphasis on time to market with successful tapeout.
Author:
• Practical UVM. Step by step with IEEE 1800.2 (Book) https://www.amazon.com/gp/product/0997789611/ 2/2020
• Practical UVM Step by Step Examples UVM 1.2 (Book) https://www.amazon.com/gp/product/0997789603/ 7/2016
• Effective Functional Verification (Book) https://www.amazon.com/gp/product/B000WFLHZU 7/2006
Co Author: “UVM and UPF: An Application of UPF Information Model” – DVCON Paper 2019
You can see recordings at http://www.accellera.org/resources/videos:
• “Introducing IEEE 1800.2 – The Next Step for UVM” – 2/27/2017
• “IEEE-Compatible UVM Reference Implementation and Verification Components” – 2/26/2018
• “Portable Test and Stimulus: The Next Level of Verification Productivity is Here” 2/26/2018
Other Activity:
• UVM Committee member since 2015; Portable Stimulus Committee member since 2017
• DVCON Vice Chair (2019, 2020), DVCON Committee TPC poster chair & TPC member (2017, 2018)
• DVCON India poster chair & TPC member (2016, 2017, 2019)
He was part of the UVM-IEEE Standardization committee for both IEEE 1800.2-2017 and IEEE-1800.2-2020 and has helped many companies with UVM methodology and best practices.