Here is the Table of Contents for this version of the book.
This book is made up of many parts. A short summary is below:
PART 1: Overview of the UVM Class Library
This part is a UVM Tutorial. It begins with a UVM Library overview introducing some concepts and classes that you will need to complete your journey through in Parts 2,3,4. Completing this Part should give you a good idea of what the UVM library contains. If you know UVM, you can look into the content of this Part for any details.
Part 2: Stitching it all together
This part attempts to bring together concepts presented in Part 1 to put together a complete verification environment. It discusses in practical detail various aspects of a UVM environment and connects master and slave verification components through a simple pass through DUT. The components and concepts developed in this chapter are reused in Part IV. The wishbone protocol is chosen instead of the UBUS protocol described in the UVM Users Guide. While it would have been possible to extend the UBUS protocol description to allow some other transfers and also create examples using actual RTL with this protocol, such an effort would be rather significant. This book instead leverages RTL IP that has been proven elsewhere to teach UVM so that you can continue learning and exploring well documented IP.
Part 3: Stimulus Generation
Creation and driving of stimuli form a crucial activity in any verification effort. The UVM class library allows the user to
write reusable code and also provides some guidelines for how to structure this code. This part covers various concepts and considerations for stimulus generation.
Part 4: Block level verification environments
Part 4 now moves on to block level verification environments. Since it was not possible to address aspects of UVM in verification in a fair amount of detail in Parts 2 and 3, Part 4 provides practical examples of integrated UVM environments while highlighting aspects of UVM.
As some RTL cores with verilog environments are available from www.opencores.org, it makes it possible for readers who are coming into ASIC verification from a design world to relate more quickly to the concepts in UVM using these cores. Hence, all environments are built around these available cores merged into an example platform. You can also choose to add other RTL cores to this design or delve into a variety of other topics in verification using these examples as a platform.
Note: While complete environments have indeed been provided to you to learn and extend from, it has not been my intention to either verify the core provided nor delve into details of each core in this book. Such an exercise is left to you hoping that you will undertake it with the intention of exploring deeper into UVM at your own pace.
The main areas of UVM covered in Part IV are:
- UVM Register modeling in context of a Video Display Unit
- The cross bar random environment in UVM is used to explain many UVM concepts with multiple components in the environment.
- Data and stimulus considerations and various sequence types for a random verification of the Ethernet MAC in UVM
- Using UVM to enhance functional coverage of a DUT in a legacy environment.
Part 5: Advanced Topics
Part V now goes into some more advanced topics in UVM that are not covered in earlier sections. Content in this part assumes you have studied the earlier four parts. Some of the main areas covered are: • Synchronization among processes in UVM
• Heartbeat applications to ensure your testbench is running • Reactive sequencer applications in UVM